Friday, September 21, 2007

Intel Touts Application Targeted Accelerators, Vague on SSE5

In spite of the fact that Advanced Micro Devices unveiled its streaming SIMD instructions 5 (SSE5) recently, the technology may not be as forward looking as previously thought. Intel Corp. believes that a superset of SSE4 will satisfy all the current requirements, whereas Application Targeted Accelerators (ATAs) available in the future chips will boost performance dramatically, perhaps, without SSE5.

The introduction of SSE4 instructions along with 45nm code-named Penryn family of processors seems to be the last major update to SSE technology from Intel. The code-named Nehalem chips will feature SSE4.2, which will add several new instructions to make accelerated string and text processing more efficient. That seems to be the final set of SSE from Intel and already in the code-named Westmere processors Intel will implement its first application targeted accelerator, which will speed up AES encryption/decryption.

Application targeted accelerators extend the capabilities of Intel architecture by adding performance-optimized, low-latency, lower power fixed-function accelerators on the processor die to benefit specific applications. Such accelerators are the start of a natural evolution of adding advantageous implementations of fixed-function capabilities to the processor, Intel said.

Just as the evolution of silicon technology from 65 nm to 45 nm to 32 nm will enable more transistors for additional cores and cache, so too will it also enable these fixed-function on-die implementations. The benefit will be greater performance – and superior energy efficiency – in processing specific applications.

Software makers will also have to use new instructions to take advantage of Intel’s ATAs, therefore, from software perspective ATAs hardly differ from SSE. At the same time, application specific accelerators is a natural evolution of multi-core processors: both Advanced Micro Devices and Intel Corp. said in the past that homogeneous cores of multi-core central processing units will evolve into arrays heterogeneous cores, some of which may be tailored to process certain types of data.

Intel did not say whether it plans to support SSE5 or not, however, the company may never implement the AMD-proposed set of streaming SIMD instructions in order not to confuse software makers who will have to choose whether to use SSE5 or ATAs.

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