Saturday, March 29, 2008

TSMC to Make Chips Using 40nm Fabrication Process

Taiwan Semiconductor Manufacturing Company, a leading contract maker of semiconductors, on Monday unveiled the foundry's first 40nm manufacturing process technology. The new fabrication process is an optical shrink of TSMC's 45nm process tech and will allow customers of the company to cut-down their manufacturing costs without significant additional investments.

"Our design flow can take designs started at 45nm and target it toward the advantages of 40nm. A lot of TSMC development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives," said John Wei, senior director of advanced technology marketing at TSMC.

The new node supports a performance-driven general purpose (40G) technology and a power-efficient low power (40LP) technology. It features a full design service package and a design ecosystem that covers verified third party IP, third party EDA tools, TSMC-generated SPICE models and foundation IPs. First wafers out are expected in the second quarter of 2008.

The 45nm node provided double the gate density of 65nm, while the new 40nm node features manufacturing innovations that enable its LP and G processes to deliver a 2.35 raw gate density improvement of the 65nm offering. The transition from 45nm to 40nm low power technology reduces power scaling up to 15%.

TSMC has developed the 40LP for leakage-sensitive applications such as wireless and portable devices and its 40G variant targeting performance applications including central processing units, graphics processing units, chips for game consoles, networking, FPGA designs and other high-performance consumer devices.

The 40nm footprint is linearly shrunk and the SRAM performance is fully maintained when compared to its 45nm counterpart, its SRAM cell size is now the smallest in the industry at 0.242┬Ám2.

The 40nm process employs a combination of 193nm immersion photolithography and extreme low-k (ELK) material. The logic family includes a low-power triple gate oxide (LPG) option to support high performance wireless and portable applications. Both the G and the LP processes offer multiple Vt core devices and 1.8V, 2.5V I/O options to meet different product requirements.

TSMC’s CyberShuttle prototyping service can be booked for 40nm designs in April, June, August, October and December this year and first wave 45/40nm customers have already used above 200 blocks on completed multi-project wafer runs. The 40G and LP processes will initially run in TSMC’s 12" wafer Fab 12 and will be transferred to Fab 14 as demand ramps.

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